SK Hynix
Research Intern
Nov 2026 – Present
Work
OuterProduct Labs
Machine Learning Intern
May 2026 – Sep 2026
- Built an agentic pipeline that turns unstructured PDFs into structured feature rows using LLMs and web search
- Built a full-stack NBA app and trained XGBoost and TabM models to predict player statistics
UCLA VAST Lab
Undergraduate Researcher
May 2025 – Present
Research on high-level synthesis and MLIR compilers for FPGA accelerators
IEEE at UCLA
Project Lead
Apr 2025 – Jun 2026
- Taught more than 130 members digital design and FPGA programming with the Vivado design suite
Projects
FPGA Digital Audio Visualizer
Feb – May 2025
- Designed and verified a real-time audio visualizer on an Altera MAX10 FPGA
- Implemented a parameterizable radix-2 FFT of up to 32,768 points on live microphone audio
- Drew the frequency bins through a double-buffered VGA controller to prevent screen tearing
Pipelined Out-of-Order RISC-V Processor
Oct – Dec 2025
- Designed a single-issue out-of-order RV32I processor with a 6-stage pipeline, branch prediction and a load-store queue
- Synthesized it on an Arty A7-100T FPGA at 100 MHz
LLM Optimization on Snapdragon 8 Elite
Nov – Dec 2025
- Placed 3rd of 20 teams by optimizing LFM2-1.2B on a Samsung S25+
- Doubled decode speed to 83 tok/s while beating baseline accuracy
Papers
Stream Swizzling
PACT 2026
Accepted
- A compiler language that lets HLS stream non-affine permutations, such as FFT bit reversal, without bank conflicts or pipeline stalls
Classes
- Computer Architecture
- Digital Logic Design
- Digital Circuits
- Digital Signal Processing
- Operating Systems
- Parallel and Distributed Computing
- Software Construction
- LLM Inference on Edge